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Dr Vishal Shah

Dr Vishal Shah

Associate Professor 

vishal dot shah at warwick dot ac dot uk
+44 (0) 24 7657 5467

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Biography

Dr Vishal Shah; Associate Professor, joined the School of Engineering at the University of Warwick in 2017 and is part of the PEATER group (Power Electronics Applications and Technology in Energy Research). He has been working in the (ultra) wide bandgap (UWBG) materials research activity and his research interests are driven by the application-led materials development. He has over 15 years’ experience developing semiconductor materials and technologies for numerous application areas including power electronics, quantum technology, photovoltaics, CMOS, MEMS and sensing. He is the director of the Warwick Cleanroom (NanoFab-RTP) and also the UK’s only Silicon Carbide (SiC) epitaxial facility at Warwick. He has written 4 patents, and published 62 journal papers, 60 conference papers, five book chapters and made over 75 conference contributions, with an h-index of 20 and over 1374 citations (Google Scholar) as of November 2024. He is PI on a combined grant portfolio of £1.6M and CI on additional grants worth £18M.

2017-Present: Associate Professor, School of Engineering, University of Warwick, UK

  • Established a Wide Bandgap Materials Laboratory, currently focussing on Silicon Carbide application-led materials development.

2015-2017: Research Scientist, Mantis Deposition, Thame, UK

  • Developed deposition tools and techniques for epitaxy, sputtering, ebeam evaporation, ion bombardment, nano-particle deposition etc.

2013-2015: Senior Research Fellow, School of Engineering, University of Warwick, UK

  • Senior researcher in a team consisting of 2 research staff and 6 PhD students within the "Underpinning Power Electronics: Devices Theme" (EP/L007010/1) project.

2009-2013: Research Fellow, Department of Physics, University of Warwick U.K.

  • Worked on the the "mK-project" (EP/F040784/1) and "platform grant" (EP/J001074/1) teams, with 2 PhD students and 10 undergraduate projects.

Research Interests

4H-SiC Power devices and CVD Epitaxy: This activity is essentially based around the epitaxy of thick (>50µm) SiC layers for high power devices, developing fundamental materials synthesis projects. PhDs within the group are available in the topic. For example:

  • Ultra high voltage (>10kV layers) on my fellowship EP/P017363/1 for HVDC technology.
  • and 3D 4H-SiC epitaxy (EP/W004291/1)

Use of 3C, 4H and 6H-SiC materials in "More the Moore" applications: Is the next logical step for implementing other technologies using SiC knowledge from power electronics

  • such as SiC for functional coatings (Innovate UK, 10073941))
  • using SiC for photoelectrochemical generation of hydrogen from water splitting (funded from EPSRC EP/X527257/1)
  • developing semi-insulating SiC for GaN integration for RF applications (CSHubJFS13 through EP/P006973/1)
  • using 3C SiC as a MEMS material, developing material for SiC sensors etc.

Analysis and reduction of defects in semiconductors: We are developing new techniques for the detection of, reduction and utilisation of defects. For example, together with the Diamond Light Source we are developing non-destructive X-ray Diffraction Topography of materials and devices. In addition, we are developing DLTS measurement of point defects in either for use in quantum applications, or improve the efficiency of power electronics.

HeteroEpitaxy: Integration of different materials together for either added functionality, scaling of current technologies or for cost reduction.

  • 3C-SiC on Si: Is an active an ongoing piece of research, 3C-SiC has the potential to be a biological material, sensing material and high temperature electronics as well. PhDsLink opens in a new window in our group to study this topic are available!
  • Si on SiC: Deposition of doped Si and Ge on SiC substrates to create layers to be used in high temperature electronics. This investigation has involved a close collaboration with P.M.Gammon and the NICHE project, funded by the Royal Academy of Engineering.
  • Si, strained-Ge on SiGe and Si: Has recently resulted in ultra-high carrier mobility structures, this research is funded by the Ge Renaissance program (EP/F031408/1) and the Si Photonics program (EP/E065317/1) and EPSRC grant EP/D034485/1.

Novel Device Fabrication Projects:

  • Power Electronics Device Fabrication: The fabrication technology for SiC is a much more harsh and power intensive when compared to Si technology, requiring high temperature anneals, gas forming of 3D structures, high power etching and electrochemical etching. These techniques all need development to enable the next efficient power device!
  • MEMS fabrication: This area of research is makes platforms which have a minimal volume and physically disconnected in a vacuum, meaning MEMS fabrication for suspended structures. Work from this programme has been submitted under two British patent applications: 1107574.4 and 1206913.4. This programme was funded by EPSRC grant EP/J001074/1

Device Characterisation: Utilising our state of the art device characterisation suite, we have been developing advanced Hall measurements, Deep Level Transient Spectroscopy (DLTS), Lifetime measurements to aid development of power electronic devices.

Projects and Grants

Selected Publications

For up to date lists please consult my Google Scholar, Scopus or ORCID

Research Facilities

The PEATER Group is one of the leading research groups in the world focused on SiC device development, with a suite of equipment and facilities to match. This includes:

  • The Science City Cleanroom, a 150 m2 ISO class 6 cleanroom including high temperature oxidation and annealling furnaces, photolithography, etching and wet processing, metal deposition, and atomic layer deposition.
  • The UK’s only industrial SiC CVD reactor in an ISO class 4 cleanroom, used for the epitaxial growth of SiC.
  • Characterisation Facilities, including a Keysight B1505A power device analyser and a SemiProbe semi-automated wafer prober for device characterisation up to 10 kV, 100 A and 300 °C.

  • An ISO class-8 packaging cleanroom.

Teaching

ES434 - ASICS, MEMS and Smart Devices

ES3E6 - Microwave Engineering and RF Circuits

ES2D6 - Semiconductor Materials and Devices

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